1. Field of the Invention
The present invention relates to a semiconductor device or a method of manufacturing a semiconductor device. Embodiments of the present invention are capable of reducing current loss in a semiconductor device by increasing the contact surface between channel and a gate. This reduction of current loss may be accomplished by improving electron mobility by manipulating lattice properties of the channel.
2. Description of the Related Art
Transistors are semiconductor devices with great utility and are necessary in modern computers. Transistors are also used in communication systems, such as telephone systems and the Internet. Over time, modern computers and communication systems have continuously improved. Improvements include the miniaturization of devices, the increase in speed of devices, and lowering of power consumption of devices. These improvements have allowed computers and telephones to be much more powerful, while also becoming more affordable.
Two techniques that are used during semiconductor device manufacturing are scaling down and integration. Scaling down and integration of semiconductor devices (e.g. transistors) may be achieved by downsizing structures of the semiconductor devices. As semiconductor devices become smaller and are downsized, more semiconductor devices can be included (i.e. integrated) in a single chip. Further, downsizing decreases the time needed for electrons to pass through a transistor, which reduces processing time of a transistor. In other words, downsizing allows a transistor to work faster. Downsizing also minimizes the quantity of electrons flowing through a transistor. By minimizing this quantity of electrons, power consumption of a transistor is also minimized.
High integration, high speed, and low electric power consumption of transistors have improved transistor performance. A minimum width of the semiconductor transistor has evolved from 10 μm in 1971, to 0.25 μm in 1997, and to 90 nm in 2003. Over the past 30 years, transistors have been downsized by a factor of about 50. Further, transistors have been integrated by a factor of about 10,000. Chip speed has improved by a factor of about 1,000. Currently, transistors having a width of about 90 nm are being researched and transistors having a width of about 65 nm are contemplated.
The following are examples of transistors with different dimensions. A transistor having a width of about 0.13 μm has a gate width of about 70 μm on a 200 mm diameter wafer. A transistor having a width of about 90 nm may have a gate width of about 50 nm on a 300 mm diameter wafer. A transistor having a width of about 65 nm may have a gate width of about 35 nm on a 300 mm diameter wafer.
There are some advantages of a process for manufacturing a semiconductor having a transistor with a width of about 90 nm over the process for manufacturing a semiconductor having a transistor with a width of about 0.13 μm. High speed and low electric power consumption transistors may be produced, based on fabrication techniques of a gate oxide layer having a thickness of about 1.2 nm, a gate having a width of about 50 nm, and utilization of strained silicon. Manufacturing costs of semiconductor devices may be reduced by using wafers having diameters of about 300 mm. Despite the rapid progress of semiconductor technology, a typical transistor in a chip remains a Metal Oxide Silicon Field Effect Transistor (MOSFET). The fundamental principle of semiconductor transistor operation (which is characterized by an equation of motion of drift diffusion of an electron as a particle) continues to govern design, despite the transistor being downsized by more than a factor of 50. In other words, the MOSFET fabrication technique is still considered when downsizing techniques are developed.
Some complications exist in fabrication techniques of MOSFETs having a width less than about 0.1 μm. For example, when a width of a transistor is about 10 nm, in view of physics, a quantum mechanical movement of electrons may dominate and the transistor may not operate. This complication may arise due to an electron in a small-scale transistor acting as an individual charge. One proposed solution to this complication is to modify the presently used MOSFET fabrication technique to reduce a short channel effect or side effects due to a quantum effect. Another proposed solution to this complication is to develop a nano-scale device involving a quantum mechanical operation theory which emerges from the classical MOSFET operation theory.
There are some obstacles in manufacturing techniques of CMOS transistors, having widths less than about 0.1 μm. These obstacles may be due to limited space charge layers, tunneling effects, and/or non-uniform doping. These obstacles may arise during lithography, forming gate oxide layers, forming shallow source/drain extensions, and/or forming halo pocket/retrograde wells in small-scale parameters. Consequently, a high permittivity gate oxide layer substitute for SiO2, a technique for improving gate delay, a technique for reducing scattering on a surface between a gate oxide layer and a channel (to increase electron mobility and maintain high driving current) have been researched without producing significant results. However, strained silicon may be used in the semiconductor device during manufacturing of a transistor having a width of about 90 nm.
FIG. 1 is an exemplary graph illustrating an increase of electron mobility using strained silicon in a semiconductor device. The graph of FIG. 1 is a result of a strained silicon semiconductor test conducted by Intel Corporation. In FIG. 1, the vertical axis represents an effective mobility and the longitudinal axis represents a vertical effective field. FIG. 1 illustrates the effective mobility of a general silicon semiconductor 10, strained silicon with silicon-germanium having about 15% germanium atom concentration 15, and strained silicon with silicon-germanium having about 20% germanium atom concentration 16.
Generally, a semiconductor device is operated in a range between about 500 and about 600K V/Cm. Silicon semiconductor 10 exhibits about 270 cm2/V°s of electron mobility. When the silicon is strained with the 15% silicon-germanium 15, the electron mobility is about 450 cm2/V°s. Likewise, when the silicon is strained with the 20% silicon-germanium 16, the electron mobility is about 480 cm2/V°s. As illustrated, when an active silicon layer is strained with a silicon-germanium epitaxial layer having about 17% germanium atom concentration, the electron mobility increases by over 70%. The semiconductor devices exhibited in FIG. 1 are tested in a two-dimensional way. A matching technique of the strained silicon with the transistor in a three-dimensional way has not been developed, prior to the present invention.
A two-dimensional method of improving the transistor speed using strained silicon in a semiconductor device has been known. In order to improve the transistor integrity and speed, it is required to reduce semiconductor device scale or develop a three-dimensional method. Reducing the semiconductor device scale has some limitations since the shape description technique for an integrated circuit has not been secured in a scale less than about 100 nm. Thus, it is preferable to adopt a three-dimensional device. When the channel width is below about 90 nm, however, a short channel effect and a current leakage through the gate oxide layer may occur. The short channel effect indicates a reduction of an effective channel length due to a diffusion of n-type or p-type impurity atoms in the channel by a heat treatment at a high temperature. When the effective channel length is reduced, a short circuit occurs between the source and the drain in the device having the gate with a minute length.
Poly gates are formed on three faces of the channel transistor in the CMOS structure. The transistor having this structure is called as a Tri-Gate device. The Tri-Gate device may decrease the short channel effect that frequently occurs in a single gate. As is described above, the Tri-Gate device using the strained silicon is very powerful for embodying the transistor having the width less than about 90 nm. However, prior to the present invention, Tri-Gate devices have not been utilized in conjunction with strained silicon.